If ECL technology can be characterized by properties such as high operating speed, (medium) high degree of integration and (medium) high dissipated power, then FET technology, having only medium operating speeds in comparison thereto, can be characterized by extremely high degree of integration and extremely low dissipated powers. These latter properties have led to efforts to provide integrated circuits in FET technology that operate in speed ranges that were previously found only in bipolar technology.
Thus, (for example, disclosed in European reference EP-A-0 262 79 corresponding to U.S. Pat. No. 4,801,936) prior art broadband signal switching equipment has a cross point matrix in FET technology whose switch elements are each respectively formed with a switching transistor that has its control electrode charged with a through-connect, or, respectively, inhibit signal and has its main electrode connected to the appertaining matrix output line. The switch elements each respectively have an auxiliary transistor that forms a series circuit with the switching transistor, this auxiliary transistor having its control electrode connected to the appertaining matrix input line and having its main electrode facing away from the series circuit connected via a sampling transistor to one terminal of the operating voltage source to whose other terminal the respective matrix output line is connected via a pre-charging transistor. The pre-charging transistor and sampling transistor (oppositely relative to one another) respectively have their control electrode charged with a switching matrix network drive clock that subdivides a bit through-connection time span into a pre-charging phase and into the actual through-connection phase. As a result, given an inhibited sampling transistor, the matrix output line in every pre-phase is at least approximately charged via the pre-charging transistor to the potential prevailing at the other terminal of the operating voltage source. This known broadband signal switching equipment that can have sampling transistors individually associated to switch elements or sampling transistors individually associated to a matrix input line or a matrix output line requires its own clock lines for driving these sampling transistors, these clock lines passing through the cross point matrix. This requires a corresponding surface area and involves a corresponding, capacitative loading of the matrix output lines. In order to guarantee an adequate resistance to noise, clock distribution and couplings between matrix input lines and matrix output lines require adequately high signal amplitudes on the matrix output lines, resulting in a relatively high power consumption.
Another known (for example, European reference EP-A-0 354 252 corresponding to U.S. Pat. No. 4,998,404) broadband signal switching equipment has a cross point matrix in FET technology whose inputs can each be respectively provided with an input driver circuit, whose outputs are respectively provided with an output amplifier circuit and whose switch elements respectively controlled by a holding memory cell are each respectively formed with a series circuit of a switching transistor that has its control electrode charged with a through-connect, respectively, inhibit signal and of an input transistor that has its control electrode connected to the appertaining matrix input line. This series circuit has the main electrode of the one transistor that faces away from the series circuit connected to the appertaining matrix output line, whereby the matrix output line is connected via a transistor to the one terminal of the operating voltage source. The main electrode of the other transistor facing away from the series circuit is continuously connected to the other terminal of the operating voltage source and the transistor series circuit of every switch element forms the cross point - associated, one branch of a differential amplifier whose other branch respectively shared by the cross points leading to one and the same output line is formed by the output amplifier circuit individually associated to matrix output line. The output amplifier circuit comprises a series circuit of a first transistor that has its control electrode line at the other terminal of the operating source and of a second transistor that has its control electrode charged with a reference voltage. This series circuit has the main electrode of the one transistor facing away from the series circuit connected to the appertaining matrix output line and has the main electrode of the other transistor that faces away from the series circuit and leads to the amplifier output connected via a load transistor to the other terminal of the operating voltage source.
This concept of a "distributed" differential amplifier requires, first, a relatively high precision of the said reference voltage and, thus, a correspondingly involved reference voltage generator; second, what is referred to as the transistor matching is also problematical for the distributed differential amplifier, i.e., offering transistors whose characteristics correspond to one another.